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Showing posts from February 7, 2021

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Resuming Pace: I Shall Not Be Pursuing a Second Bachelor's Degree

On May the 5th, 2021, I used a strong position deciding my pursuit of a second Bachelor’s degree: my choice was the University of Maryland Global Campus (UMGC, link ), but I decided to resume my Master’s program, by itself.  Let me explain with Scripture: the Gospel of Jesus Christ According to Matthew, specifically. In ancient times, records of a man called Jesus the Christ were written. Among these records was a Gospel, According to Matthew, of Jesus Christ. According to legend, Jesus Christ stated, “Blessed are the meek: for they shall inherit the earth (KJV, Matthew 5:5, link ).” Jesus the Christ was saying those who are submissive shall inherit the earth rather than those who are brash.  In my attempt at starting a second Bachelor’s program, I eventually realized I had been too pushy: I wanted the May 19th start date, and I wanted the admission process expedited, I wanted ease of access between majors, I wanted advantages to the application process because of what UMGC (I was gra

Register Nomenclature and Renaming

On the subjects, registers and register names, scarce information, it seems, regards their origin. However, in August 2020, Siva Nishok Dhanuskodi, Samuel Allen, and Daniel E. Holcomb wrote an article, Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET. Dhanuskodi, et. al., wrote, “Recent works show that subround architectures are especially susceptible to side-channel attacks. In response to this, we extend the register renaming technique to enable microarchitectural randomization of subround AES implementations to mitigate side-channel leakage” (Dhanuskodi, et. al., Aug 2020). For a security purpose, mitigating side-channel attacks, Dhanuskodi, et. al. were saying that they had the validation and verification to rename registers. In this case, the security regarded Advanced Encryption Standard, AES, implementations, a rather powered security protocol.             On 26 June, 2019, ATP Electronics explained the relevance that AES has. ATP E

On Computer Organization and Architecture: the Hierarchy

On, Abirami Thangavel wrote Superscalar & VLIW Architectures: Characteristics, Limitations & Functions. Regarding parallel architectures, superscalar and VLIW, Thangavel wrote: In computer architecture, parallel processing refers to processing of multiple instructions of a program by distributing them among multiple processors. Superscalar and Very Long Instruction Word (VLIW) are parallel architectural models based on Flynn's Taxonomy. Both superscalar and VLIW architectures are capable of executing multiple instructions at one cycle. Each uses a different method for instruction scheduling. While superscalar processors execute instructions dynamically, VLIW uses static scheduling of program instructions.[1] Thangavel was saying this: on Flynn’s Taxonomy, superscalar and VLIW architectures are based, but they have differences. Therefore, on entity priorities, entities have different descriptive capabilities. As follows, a superscalar processor is this: a microproc

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